Systematic design of RSSI and logarithmic amplifiers circuits

This paper presents a systematic design methodology for logarithmic amplifiers and receiver signal strength indicator (RSSI) circuits. A close expression for the maximum detection error using a piece wise linear approximation of the logarithmic function was derived. The design methodology has been proposed that optimizes the power consumption and 3 dB bandwidth of a single stage CMOS limiting amplifier according to the common mode voltages in order to meet the voltage gain and detection error requirements. The results for the RSSI circuit indicate 70 dB dynamic range, 3 dB bandwidth of 500 MHz and maximum detection error of 0.6 dB in the temperature range between -40°C and +70°C. The overall power consumption equals to 10.3 mW in 180 nm CMOS process technology.