DocumentCode
3201730
Title
H.264 Intra Prediction Architecture Optimization
Author
Wang, Shao-Bo ; Xiao-Lin Zhang ; Yao, Yuan ; Wang, Zhe
Author_Institution
Beihang Univ., Beijing
fYear
2007
fDate
2-5 July 2007
Firstpage
1571
Lastpage
1574
Abstract
This paper proposes an optimized H.264 intra prediction arithmetic to reduce the time required to complete the intra prediction by saving ninety percent waste time during the process of intra prediction. Firstly, the 16times16 luminance prediction can be decomposed equally into 16 parts and inserted into the same macro-block´s 4x4 luminance prediction to save the 16times16 luminance prediction time in one macro-block´s luminance prediction. Then, by means of changing the computation sequence of 4times4 luminance prediction, a large amount of waiting time between 4times4 blocks´ luminance predictions can be further removed. Almost all the waste time can be reused or eliminated by these optimizations. At the last part of this paper, an optimized hardware implementation aiming at fitting to the whole H.264 video coding system and a method to realize 16times16 luminance DC prediction on it are proposed.
Keywords
image sequences; optimisation; pipeline arithmetic; video coding; FPGA; H.264 intra prediction architecture optimization; luminance prediction; pipeline processing; video coding; video sequence; Arithmetic; Discrete cosine transforms; Encoding; Hardware; Internet; MPEG 4 Standard; Optimization methods; Video coding; Video compression; Videoconference;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia and Expo, 2007 IEEE International Conference on
Conference_Location
Beijing
Print_ISBN
1-4244-1016-9
Electronic_ISBN
1-4244-1017-7
Type
conf
DOI
10.1109/ICME.2007.4284964
Filename
4284964
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