A Cost-Effective VLSI Architecture of VLD for MPEG-2 and AVS

In this paper, a cost-effective architecture of variable length decoder (VLD) for MPEG-2 and AVS (advanced audio video coding standard established in China, Part two, Ji Zhun Profile) is proposed. Inverse scan (IScan) and inverse quantisation (IQ) are also merged into this design for cost-effective implementation. A novel group-based architecture with efficient symbol generation scheme is presented for MPEG-2 and a new memory-efficient architecture with mixed memory organization is presented for AVS. Furthermore, we analyze the algorithms of the two standards and propose a merged IQ scheme and a merged RAMs scheme. The proposed design consumes about 13.5 K gates at a clock constrain of 166 MHz with 0.18 mum CMOS technology. The simulation results show that it can achieve real-time decoding, such as HDIO8O1 (1920x1088@30 MHz) format video of AVS and MPEG-2.