VHDL implementations of fast IC testing tools

Author

Ryan, Christopher A.

Author_Institution

Dept. of Electr. Eng., Kentucky Univ., Lexington, KY, USA

fYear

1995

fDate

8-10 Aug. 1995

Firstpage

80

Lastpage

83

Abstract

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing fast approximate switch-level fault simulation. Results show one order of magnitude of complexity speed-up as compared to traditional fault simulation techniques, while maintaining good accuracy.

Keywords

MOS logic circuits; automatic testing; fault diagnosis; hardware description languages; integrated circuit testing; logic testing; multivalued logic circuits; IC testing tools; MOS logic; VHDL implementations; accuracy; complexity speed-up; multivalued logic; simulation times; switch-level fault simulation; Circuit faults; Circuit simulation; Integrated circuit modeling; Integrated circuit testing; Logic; Mathematical model; Observability; Signal resolution; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

AUTOTESTCON '95. Systems Readiness: Test Technology for the 21st Century. Conference Record

Conference_Location

Atlanta, GA, USA

Print_ISBN

0-7803-2621-0

Type

conf

DOI

10.1109/AUTEST.1995.522657

Filename

522657