DocumentCode
3202985
Title
Design and modeling of on-chip electrostatic discharge (ESD) protection structures
Author
Liou, Juin J. ; Gao, Xiaofang
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Central Florida, Orlando, FL, USA
Volume
2
fYear
2004
fDate
16-19 May 2004
Firstpage
619
Abstract
Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a computer-aided design tool for ESD protection design and applications. Specifically, we develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. Experimental data measured from the transmission line pulsing (TLP) technique and human body model (HBM) tester are included in support of the model.
Keywords
SPICE; electrostatic discharge; equivalent circuits; integrated circuit design; integrated circuit reliability; Cadence SPICE; ESD circuit simulation; computer-aided design too; critical reliability concern; human body model; microchips; on-chip electrostatic discharge protection structures; transmission line pulsing technique; Application software; Biological system modeling; Circuit simulation; Design automation; Electrostatic discharge; Electrostatic measurements; Protection; Robustness; SPICE; Standards development;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2004. 24th International Conference on
Print_ISBN
0-7803-8166-1
Type
conf
DOI
10.1109/ICMEL.2004.1314905
Filename
1314905
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