DocumentCode
3203033
Title
The concepts, methods and technics for the electronic testability implementation
Author
POPA, Ilie ; Lita, Ioan ; Chita, Anca Monica
Author_Institution
Electron. Dept., Pitesti Univ., Romania
fYear
2001
fDate
2001
Firstpage
263
Lastpage
267
Abstract
The first part of the paper briefly describes the necessity of testability and the design-for-test concept. The testability problem is presented at the integrated circuit, printed circuit board layout and electronics module levels. In the second part, several very important strategies for testability development are proposed (in nine stages). As applications, testing practice problems are presented, including testing of printed circuit board and link connections (connection interrupts or unsoldered connections, short-circuit to GND), and testing of circuit board connectors (connector with broken or bent pin, network terminator fault, conflict on the network). The final part of the paper presents a system for verification of component positioning on the board by image acquisition and processing (orientation, correct value and type of component, correct solders)
Keywords
assembling; design for testability; electric connectors; image processing; integrated circuit design; integrated circuit packaging; integrated circuit testing; modules; position control; printed circuit accessories; printed circuit design; printed circuit testing; production testing; soldering; bent connector pin; broken connector pin; circuit board connector testing; component orientation; component positioning verification system; component type; component value; connection interrupts; design-for-test concept; electronic testability implementation; electronics module level testability; image acquisition; image processing; integrated circuit level testability; link connection testing; network conflict; network terminator fault; printed circuit board connection testing; printed circuit board layout level testability; short-circuit; solders; testability; testability development strategies; testing practice; unsoldered connections; Application specific integrated circuits; Circuit testing; Design for testability; Electronic equipment testing; Integrated circuit layout; Integrated circuit testing; Life testing; Logic testing; Manufacturing; Printed circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Technology: Concurrent Engineering in Electronic Packaging, 2001. 24th International Spring Seminar on
Conference_Location
Calimanesti-Caciulata
Print_ISBN
0-7803-7111-9
Type
conf
DOI
10.1109/ISSE.2001.931076
Filename
931076
Link To Document