A word-line boost driver design for low operating voltage 6T-SRAMs

Low voltage operated embedded SRAMs in nanometric CMOS technologies are sensitive to PVT variations and hence can cause poor yield. In this paper, we exploit the concept of Dynamic Noise Margin (DNM) to enhance the 6TSRAM cell design flexibility and reliability. In particular, a transition Word-line driver (WL) boost circuit design is proposed. Carried-out post layout Monte Carlo simulations on a 400 mV, 4 Kbit 6T SRAM sub array in TSMC 65nm CMOS technology show the benefit of proposed scheme. A 28.5% improvement in the developed bitline differential voltage and a 39% reduction in cell leakage current are achieved.