Architecture for increased address space in an ultra-low-power microprocessor

Sensor systems face the conflicting requirements of low power consumption and relatively large storage space. We have implemented a hybrid Instruction Set Architecture (ISA) that maintains the advantages of a 16-bit datapath while increasing the address space from 65 KB to 2 MB by using 24 address bits. The address space is supported by an extended 24-bit program counter and sixteen 24-bit registers. Compared to a hypothetical 16-bit implementation, static power increases by only 3% and measured data indicates that writing an additional 8 bits (with maximum bit-flipping) requires only 0.7% of single-cycle active energy. The active energy used by a 24-bit adder is not significantly higher than a 16-bit adder if the upper bits do not change from cycle to cycle. In addition, a unique combination of addressing modes minimizes code expansion due to the small instruction size.