Register transfer low power design based on controller decomposition

Resent investigations have shown the very good results of digital system; and circuits optimization using integration of dynamic power management in the design flow. This approach proceed from detection periods of time during which parts of the circuit are not doing useful work and shut them down by either turning off the power supply or the clock signal. In this work, we take this approach to design at register transfer level, We consider the partition technique for controller and datapath simultaneously and develop a decomposition procedure for the finite state machines with data-path model. The proposed technique leads to a general low power design methodology based on functional partitioning of initial specification.