All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter

This paper presents the all-digital phase-locked loop (ADPLL) with the local passive interpolation time-to-digital converter (LPI-TDC). Unlike the conventional LPI-TDC, the proposed TDC has a tristate inverter delay cell in only first delay chain, other delay cell is composed of only normal inverters that have same delay as tristate inverter. LPI-TDC based a tristate has the advantages of higher resolution than conventional LPI-TDC. The resolution of the proposed LPI-TDC increases by approximately 1.5 times compare to the conventional LPI-TDC. The proposed ADPLL has been implemented using 0.18μm CMOS process. The peak to peak jitter is 32.86ps, and the power consumption of the ADPLL is 25.02mW, which is lower than the conventional ADPLL, at 600 MHz operation with 1.8V power supply voltage.