• DocumentCode
    3204525
  • Title

    FPGA based device specific key generation method using Physically Uncloanble Functions and neural networks

  • Author

    Pappala, Swetha ; Niamat, Mohammed ; Sun, Weiqing

  • Author_Institution
    Electr. Eng. & Comput. Sci., Univ. of Toledo, Toledo, OH, USA
  • fYear
    2012
  • fDate
    5-8 Aug. 2012
  • Firstpage
    330
  • Lastpage
    333
  • Abstract
    The fierce competition in today´s global market has made trustworthy authentication an essential aspect for the implementation of valuable designs. FPGAs, in particular, need built-in security not only to prevent reverse engineering but also to prevent hacking and cloning. To counter such threats, methodologies for preventing IC piracy have been developed that require a unique signature key for every fabricated chip. Physically Unclonable Functions are circuits that are capable of generating a unique signature for a given IC. This paper presents a design for trustworthy authentication of an FPGA taking advantage of its unique architecture. The PUFs are implemented on Xilinx Spartan XC2S100 FPGAs. Intra chip and Inter chip responses are analyzed to determine the extent of uniqueness of the PUF responses. Hamming distances for 128 bit responses are calculated and represented graphically. The uniqueness of the responses is calculated as 49.0625%. This work also involves an error correction process using bidirectional associative memories to correct the error bits occurring due to considerable changes in temperature and other environmental factors. The proposed method yields better results and also reduces the computational complexity compared to conventionally used codes like BCH codes. The proposed method drives the failure rates below 1 ppm.
  • Keywords
    content-addressable storage; field programmable gate arrays; logic design; neural nets; security of data; FPGA; Hamming distance; IC piracy; Interchip response; bidirectional associative memories; built-in security; cloning; device specific key generation method; error correction process; hacking; intrachip response; neural network; physically unclonable function; trustworthy authentication; Error correction; Field programmable gate arrays; Multiplexing; Oscillators; Security; Table lookup; Vectors; Bidirectional Associative Memory; Error Correcting Code; Field Programmable Gate Arrays; Neural Network; Physically Unclonable Functions; Security; Supervised Learning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
  • Conference_Location
    Boise, ID
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4673-2526-4
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2012.6292024
  • Filename
    6292024