• DocumentCode
    3204655
  • Title

    A Very Fast Simulator for Exploring the Many-Core Future

  • Author

    Certner, Olivier ; Li, Zheng ; Raman, Arun ; Temam, Olivier

  • Author_Institution
    ST Microelectron., INRIA Saclay, Orsay, France
  • fYear
    2011
  • fDate
    16-20 May 2011
  • Firstpage
    443
  • Lastpage
    454
  • Abstract
    Although multi-core architectures with a large number of cores ("many-cores\´\´) are considered the future of computing systems, there are currently few practical tools to quickly explore both their design and general program scalability. In this paper, we present SiMany, a discrete-event-based many-core simulator able to support more than a thousand cores while being orders of magnitude faster than existing flexible approaches. One of the difficult challenges for a reasonably realistic many-core simulation is to model faithfully the potentially high concurrency a program can exhibit. SiMany uses a novel virtual time synchronization technique, called spatial synchronization, to achieve this goal in a completely local and distributed fashion, which diminishes interactions and preserves locality. Compared to previous simulators, it raises the level of abstraction by focusing on modeling concurrent interactions between cores, which enables fast coarse comparisons of high-level architecture design choices and parallel programs performance. Sequential pieces of code are executed natively for maximal speed. We exercise the simulator with a set of dwarf-like task-based benchmarks with dynamic control flow and irregular data structures. Scalability results are validated through comparison with a cycle-level simulator up to 64 cores. They are also shown consistent with well-known benchmark characteristics. We finally demonstrate how SiMany can be used to efficiently compare the benchmarks\´ behavior over a wide range of architectural organizations, such as polymorphic architectures and network of clusters.
  • Keywords
    discrete event simulation; multiprocessing programs; multiprocessing systems; synchronisation; SiMany; discrete-event-based many-core simulator; dwarf-like task-based benchmarks; dynamic control flow; irregular data structures; multicore architectures; network of clusters; polymorphic architectures; spatial synchronization; virtual time synchronization; Accuracy; Computer architecture; Hardware; Programming; Synchronization; System recovery;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing Symposium (IPDPS), 2011 IEEE International
  • Conference_Location
    Anchorage, AK
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-61284-372-8
  • Electronic_ISBN
    1530-2075
  • Type

    conf

  • DOI
    10.1109/IPDPS.2011.50
  • Filename
    6012814