Reliability analysis of a Reed-Solomon decoder

Due to the shrinking of dimension and decreasing of the supply voltage, processors based on deep submicron technologies are more susceptible to defects and errors. This paper presents a model to simulate the behavior of the Reed-Solomon decoder prone to transient faults. The simulation environment developed allows to analyze the influence of the different blocks on the reliability of the decoder. Identifying the most critical blocks of the processor allows the designer to implement a selective hardening strategy and then to minimize the additional costs associated to improve fault tolerance.