Reducing test point overhead with don´t-cares

Test points provide additional control to design logic and can improve circuit testability. Traditionally, test points are activated by a global test enable signal, and routing the signal to the test points can be costly. To address this problem, we propose a new test point structure that utilizes controllability don´t-cares to generate local test point activation signals. To support the structure, we propose new methods for extracting don´t-cares from assertions and finite state machines in the design. Our empirical evaluation shows that don´t-cares exist in many designs and can be used for reducing test point overhead.