Low-spur technique for Integer-N phase-locked loop

In this paper, we presents a low-spur phase locked loop (PLL) system for wireless applications. The low-spur frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage-controlled oscillator (VCO) in order to reduce the reference spur at the output of the PLL. A new random clock generator is presented to perform a random selection of phase frequency detector (PFD) control for charge pump at locked state. The proposed frequency synthesizer was fabricated in TSMC 0.18-μm CMOS process. The PLL has achieved the phase noise of -105 dBc/Hz at 1MHz offset frequency and reference spurs below -72dBc.