DocumentCode
3205977
Title
Reducing thermal hotspots in microprocessors with expanded component sizing
Author
Eratne, Savithra ; John, Eugene ; Lee, Byeong
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Texas at San Antonio, San Antonio, TX, USA
fYear
2012
fDate
5-8 Aug. 2012
Firstpage
635
Lastpage
638
Abstract
Thermal hotspots are a destructive phenomenon occurring in contemporary microprocessors. High power density of microprocessors and excessive use of certain microprocessor components by applications are considered the primary causes of increased temperature. Dynamic Thermal Management Techniques used in mitigating excessive temperatures results in throttling of clock speed, which degrades the performance of the microprocessor. In this paper we propose a simple but novel technique to reduce hotspots in microprocessors. We propose to lower the power density of selected high temperature components by increasing the chip area of that component. We select thermally susceptible components that have small footprints and increase the area of such components, thereby reducing the occurrence of hotspots. The overall chip area increase is minimal and our research has shown that the associated delay penalty is negligible.
Keywords
delays; microprocessor chips; thermal management (packaging); associated delay penalty; chip area; clock speed; dynamic thermal management; expanded component sizing; microprocessors; power density; thermal hotspots reduction; thermally susceptible components; Density measurement; Microprocessors; Multicore processing; Power dissipation; Power system measurements; Transistors; Hotspot reduction; Thermal Hotspots; low power VLSI; silicon area sizing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
Conference_Location
Boise, ID
ISSN
1548-3746
Print_ISBN
978-1-4673-2526-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2012.6292100
Filename
6292100
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