Hardware implementation of JPEG2000 encoder for video compression

JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for the present wireless and Internet age. These features are possible due to adaptation of discrete wavelet transform, fractional bit plane coding and arithmetic coding. All the three algorithms are computationally intensive and require substantial number of memory and arithmetic operations. In this paper we propose a system level architecture capable of encoding JPEG2000 algorithm. For discrete wavelet transform (DWT), a lifting based DWT core for lossy compression is proposed which reduces the hardware cost and achieves the higher hardware utilization. For embedded block coding with optimized truncation (EBCOT), column-based coding architecture of tier-1 block coding engine is discussed. The system architecture has been implemented using VHDL and synthesized for Xilinx Virtex-II FPGA with estimated frequency of 50 MHz.