High speed area efficient configurable Viterbi Decoder for WiFi and WiMAX systems

Author

Nandula, Sridhar ; Rao, Yepuri Sudhakara ; Embanath, Siva Prasad

fYear

2007

fDate

25-28 Nov. 2007

Firstpage

1396

Lastpage

1399

Abstract

In this paper, an area efficient configurable design for high speed Viterbi decoder suitable for IEEE 802.11 based wireless LAN and IEEE 802.16e based WiMAX has been proposed. This design also supports the puncturing schemes defined in the above wireless standards. An area efficient VLSI design for trace back unit has been proposed in this paper. Synthesis results targeting FPGA and ASIC are included. These results show that the new architecture can achieve good speed, while offering significant area advantage.

Keywords

Viterbi decoding; WiMax; application specific integrated circuits; field programmable gate arrays; wireless LAN; ASIC; FPGA; VLSI; WiFi; WiMAX systems; high speed area efficient configurable Viterbi decoder; wireless LAN; Application specific integrated circuits; Convolutional codes; Field programmable gate arrays; Forward error correction; Hamming distance; Intelligent systems; Maximum likelihood decoding; Viterbi algorithm; WiMAX; Wireless communication; ACS; ASIC; BER; BMG; FPGA; Wi-Fi; WiMAX;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent and Advanced Systems, 2007. ICIAS 2007. International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-1355-3

Electronic_ISBN

978-1-4244-1356-0

Type

conf

DOI

10.1109/ICIAS.2007.4658614

Filename

4658614