DocumentCode
3207160
Title
Thread-safe dynamic binary translation using transactional memory
Author
Chung, Jaewoong ; Dalton, Michael ; Kannan, Hari ; Kozyrakis, Christos
Author_Institution
Comput. Syst. Lab., Stanford Univ., Stanford, CA
fYear
2008
fDate
16-20 Feb. 2008
Firstpage
279
Lastpage
289
Abstract
Dynamic binary translation (DBT) is a runtime instrumentation technique commonly used to support profiling, optimization, secure execution, and bug detection tools for application binaries. However, DBT frameworks may incorrectly handle multithreaded programs due to races involving updates to the application data and the corresponding metadata maintained by the DBT. Existing DBT frameworks handle this issue by serializing threads, disallowing multithreaded programs, or requiring explicit use of locks. This paper presents a practical solution for correct execution of multithreaded programs within DBT frameworks. To eliminate races involving metadata, we propose the use of transactional memory (TM). The DBT uses memory transactions to encapsulate the data and metadata accesses in a trace, within one atomic block. This approach guarantees correct execution of concurrent threads of the translated program, as TM mechanisms detect and correct races. To demonstrate this approach, we implemented a DBT-based tool for secure execution of x86 binaries using dynamic information flow tracking. This is the first such framework that correctly handles multithreaded binaries without serialization. We show that the use of software transactions in the DBT leads to a runtime overhead of 40%. We also show that software optimizations in the DBT and hardware support for transactions can reduce the runtime overhead to 6%.
Keywords
multi-threading; software maintenance; software tools; bug detection tools; dynamic information flow tracking; multithreaded programs; runtime instrumentation technique; software transactions; thread-safe dynamic binary translation; transactional memory; Application software; Buffer overflow; Data security; Hardware; Information security; Instruments; Laboratories; Runtime; Software tools; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th International Symposium on
Conference_Location
Salt Lake City, UT
ISSN
1530-0897
Print_ISBN
978-1-4244-2070-4
Type
conf
DOI
10.1109/HPCA.2008.4658646
Filename
4658646
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