IC chip design and synthesis for color matrixing and convolution

An Enhanced ASIC which performs both 3×3 matrix multiplication and 3×3 digital convolution was designed using VHDL. The same chip was compiled and synthesized using Synopsys. The Slack, cell area, power and timing are found by invoking commands in Synopsys. The previous version [1] was implemented on 2 μm CMOS technology which had an operation speed of 14.3 MHz The proposed ASIC is implemented in 0.12μm CMOS technology. The initial speed was found to be 181 MHz and furthermore enhanced to 307.6 MHz using optimization techniques. The multipliers and adders used in this proposed architecture are pipelined when compared with the previous version [1]. The ASIC has a latency of 7 clock cycles.