• DocumentCode
    3207704
  • Title

    A fast fractional motion estimation algorithm and architecture for H.264/AVC multiview video coding

  • Author

    Yuan-Teng Chang ; Wen-Hao Chung

  • Author_Institution
    Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
  • fYear
    2012
  • fDate
    5-8 Aug. 2012
  • Firstpage
    984
  • Lastpage
    987
  • Abstract
    This paper presents a fast fractional motion estimation (FME) and the associated VLSI architecture for H.264/AVC multiview video coding. The proposed FME automatically turns off the mode P8×8 by exploiting the results of integer motion estimation and similarity between views. In addition, the fraction-pel refinement of integer motion or disparity vector in any partition may be skipped according to the difference of their rate-distortion cost. This algorithm accelerates the FME by nearly 50% with negligible PSNR degradation and bitrate increase. The resultant FME can process a macroblock within 612 clock cycles, enough to achieve real-time coding for the stereoscopic HD1080p video sequences operating at frequency of 300 MHz.
  • Keywords
    VLSI; image sequences; motion estimation; stereo image processing; video coding; FME; H.264-AVC multiview video coding; PSNR degradation; associated VLSI architecture; fast FME; fast fractional motion estimation algorithm; frequency 300 MHz; integer motion estimation; integer motion fraction-pel refinement; rate-distortion cost; stereoscopic HD1080p video sequences; Bit rate; Complexity theory; Computer architecture; Motion estimation; PSNR; Vectors; Video coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on
  • Conference_Location
    Boise, ID
  • ISSN
    1548-3746
  • Print_ISBN
    978-1-4673-2526-4
  • Electronic_ISBN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2012.6292187
  • Filename
    6292187