Temperature effect on delay for low voltage applications [CMOS ICs]

Author

Daga, J.-M. ; Ottaviano, E. ; Auvergne, D.

Author_Institution

LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

1998

fDate

23-26 Feb 1998

Firstpage

680

Lastpage

685

Abstract

This paper presents one of the first analysis of the temperature dependence of CMOS integrated circuit delay at low voltage. Based on a low voltage extended Sakurai´s α-power current law, a detail analysis of the temperature and voltage sensitivity of CMOS structure delay is given. Coupling effects between temperature and voltage are clearly demonstrated. Specific derating factors are defined for the low voltage range (1-3 V_TO). Experimental validations are obtained on specific ring oscillators integrated on a 0.7 μm process by comparing the temperature and voltage evolution of the measured oscillation period to the calculated ones. A low temperature sensitivity operating region has been clearly identified and appears in excellent agreement with the expected calculated values

Keywords

CMOS digital integrated circuits; delays; integrated circuit modelling; sensitivity analysis; thermal analysis; α-power current law; 0.7 micron; 1 to 3 V; CMOS IC delay; CMOS integrated circuit; coupling effects; derating factors; low voltage applications; oscillation period; ring oscillators; temperature effect; temperature sensitivity; voltage sensitivity; Circuits; Degradation; Delay effects; Electrical capacitance tomography; Energy dissipation; Low voltage; Power dissipation; Temperature dependence; Temperature sensors; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 1998., Proceedings

Conference_Location

Paris

Print_ISBN

0-8186-8359-7

Type

conf

DOI

10.1109/DATE.1998.655931

Filename

655931