A cancellation technique for output-dependent delay differences in high-accuracy DACs

For high-accuracy digital-to-analog converter (DAC), delay difference depending on output voltage is one of the major nonlinearities that deteriorate the dynamic performance. In this paper, an improved output-dependent delay cancellation (ODDC) technique is proposed. The proposed ODDC is implemented in simple circuit architecture and has advantages of significant improvement on the dynamic performance in a wide frequency range without increasing the noise floor. ODDC can eliminate the switching instant variations caused by output voltage of DAC through tuning the bulk voltage of switches in the deep N-well. The algorithm of ODDC technique is derived. A 1GS/s 14 bits current-steering DAC with proposed ODDC is simulated and the SFDR can be improved significantly with proper circuit parameters.