Complexities in DSP software compilation: performance, code size, power, retargetability

The paper presents a new methodology for software compilation for embedded DSP systems. Although it is well known that conventional compilation techniques do not produce high quality DSP code, few researchers have addressed this area. Performance, estimated power dissipation, and code size are important design constraints in embedded DSP design. New techniques for code generation targeting DSP processors are introduced and employed to show improvements and applicability to different fixed point and floating point DSP popular architectures. Code is generated in fast CPU times and is optimized for minimum code size, energy dissipation, or maximum performance. Code generated for realistic DSP applications provide performance and code size improvements of up to 118% and measured power improvements of up to 49% for popular DSP processors compared to previous research and a commercial compiler. This research is important for industry since DSP software can be efficiently generated, with constraints on code size, performance, and energy dissipation