• DocumentCode
    3209303
  • Title

    Virtualizing transactional memory

  • Author

    Rajwar, Ravi ; Herlihy, Maurice ; Lai, Konrad

  • Author_Institution
    Microarchit. Res. Lab., Intel Corp., Santa Clara, CA, USA
  • fYear
    2005
  • fDate
    4-8 June 2005
  • Firstpage
    494
  • Lastpage
    505
  • Abstract
    Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from well-known limitations, so researchers have considered nonblocking transactions as an alternative. Recent hardware proposals have demonstrated how transactions can achieve high performance while not suffering limitations of lock-based mechanisms. However, current hardware proposals require programmers to be aware of platform-specific resource limitations such as buffer sizes, scheduling quanta, as well as events such as page faults, and process migrations. If the transactional model is to gain wide acceptance, hardware support for transactions must be virtualized to hide these limitations in much the same way that virtual memory shields the programmer from platform-specific limitations of physical memory. This paper proposes virtual transactional memory (VTM), a user-transparent system that shields the programmer from various platform-specific resource limitations. VTM maintains the performance advantage of hardware transactions, incurs low overhead in time, and has modest costs in hardware support. While many system-level challenges remain, VTM takes a step toward making transactional models more widely acceptable.
  • Keywords
    digital storage; memory architecture; multiprocessing programs; storage allocation; virtual storage; concurrent programs; conventional lock-based synchronization; hardware transaction; lock-based mechanism; nonblocking transaction; physical memory; platform-specific resource limitation; synchronization complexity; transaction hardware support; transactional memory virtualization; user-transparent system; virtual memory; virtual transactional memory; Computer architecture; Delay; Hardware; Microarchitecture; Programming profession; Proposals; Read-write memory; Scheduling; Switches; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 2005. ISCA '05. Proceedings. 32nd International Symposium on
  • ISSN
    1063-6897
  • Print_ISBN
    0-7695-2270-X
  • Type

    conf

  • DOI
    10.1109/ISCA.2005.54
  • Filename
    1431581