DocumentCode :
3209445
Title :
Clearing the clutter: Unified modeling and verification methodology for system level hardware design
Author :
Watanabe, Yosinori ; Swan, Stuart
Author_Institution :
Cadence Design Syst., Berkeley, CA, USA
fYear :
2012
fDate :
16-17 July 2012
Firstpage :
21
Lastpage :
23
Abstract :
The state-of-the-art design practice for complex SoCs employs multiple models of hardware components with different use cases. The cost of building and maintaining those models is high, and verifying the consistency among those models is time consuming. This paper highlights needs and issues of creating these models, and presents emerging approaches for developing solutions to address the issues.
Keywords :
formal verification; integrated circuit design; system-on-chip; clutter clearance; complex SoC design; hardware component model; system level hardware design; unified modeling; verification methodology; Clutter; Computational modeling; Hardware; Software; Solid modeling; System-on-a-chip; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Formal Methods and Models for Codesign (MEMOCODE), 2012 10th IEEE/ACM International Conference on
Conference_Location :
Arlington, VA
Print_ISBN :
978-1-4673-1314-8
Type :
conf
DOI :
10.1109/MEMCOD.2012.6292296
Filename :
6292296
Link To Document :
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