Improving processor utilization with a task classification model based application specific hard real-time architecture

Modern microprocessors with caches and pipelines show increasing performance, but at the price of a decreasing predictability of execution times. The design of hard real time systems however has to be based on worst case considerations. Consequently, real-time systems are generally oversized and fail to profit of developments in the standard processor field. This paper presents an approach where real-time systems are analyzed and built according to a task classification model. Each class of tasks corresponds to a type of processor best suited in terms of performance and deterministic execution times. The resulting target architecture framework is a tightly coupled heterogeneous multiprocessor system based on templates using off-the-shelf components. The described real-time system design process includes a schedulability analysis method that supports the partitioning and allocation process and provides the necessary real-time guarantees. The result is a event-driven hard real-time system with improved processor utilization that will provably meet all its deadlines. A rapid prototyping platform implementing this concept is presented as well as application examples