A low-power 16-bit 500 kS/s ADC

Author

Guo, Haidong ; Rector, David M. ; La Rue, George S.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA

fYear

2005

fDate

15-15 April 2005

Firstpage

84

Lastpage

87

Abstract

A 6.2 mW 16-bit 500 kSps charge redistribution self calibrating successive approximation analog-to-digital converter (ADC) is described. It has an input range of 2 V, a resolution of 16 bits and operates with +/- 1.5 V supplies. Simulations show a signal-to-noise ratio of 95 dB for an effective accuracy of 15 bits in 0.25 mum CMOS technology. A novel interleaving architecture and an improved comparator design contribute to reducing the power while maintaining the accuracy and speed. The ADC is intended to digitize the amplified neurophysiological signals from a companion 16-channel sensor IC

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit design; low-power electronics; 0.25 micron; 16 bit; 16-channel sensor IC; 6.2 mW; CMOS technology; analog-to-digital converter; charge redistribution; comparator design; interleaving architecture; neurophysiological signal; signal-to-noise ratio; successive approximation; Analog integrated circuits; Analog-digital conversion; CMOS technology; Calibration; Integrated circuit noise; Interleaved codes; MIM capacitors; Power dissipation; Sensor arrays; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on

Conference_Location

Boise, ID

Print_ISBN

0-7803-9072-5

Type

conf

DOI

10.1109/WMED.2005.1431628

Filename

1431628