Title :
Application of yield models for semiconductor yield improvement
Author :
Dance, Daren L. ; Jarvis, Richard
Author_Institution :
SEMATECH, Austin, TX, USA
Abstract :
Yield models may be applied to increase the yield learning rate in semiconductor manufacture. Detailed equipment models can be used to predict the defect-limited yield from estimates of particles added per wafer pass. These general yield models may be refined to reflect specific processes, equipment, and design rules in more accurate critical area estimates. After validation, refined models can be applied to direct particle reduction and yield improvement efforts amid conflicting priorities. Yield improvements have been demonstrated by applying defect-limited yield models in a production manufacturing facility
Keywords :
semiconductor device manufacture; semiconductor process modelling; critical area estimates; defect-limited yield; design rules; direct particle reduction; equipment models; production manufacturing facility; semiconductor manufacture; semiconductor yield improvement; wafer pass; yield learning rate; yield models; Acceleration; Continuous improvement; Inspection; Manufacturing; Microelectronics; Predictive models; Production; Semiconductor device manufacture; Semiconductor device modeling; Yield estimation;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2837-5
DOI :
10.1109/DFTVS.1992.224349
