New dynamic body biasing NMOS network technique for subthreshold Domino circuits

Body biasing technique is promising solution for speed enhancement in subthreshold domino (Sub-Domino) logics. There are five common methods for body biasing in order to increase speed in Sub-Domino logics by using of single power supply. However, this benefit can be achieved with drawback of increasing power consumption. In this paper, we propose a circuit that uses of one power supply while reduces both power and delay at the same time. The main idea of this technique is dynamic change of body voltage for NMOS network and using one stack transistor for reduction of power consumption. Simulation results show that the power consumption of the proposed design can be reduced by 40.57% and 32.78% while improving the speed by 31.35% and 65.18% speed as compared to best common method for body biasing and standard Sub-Domino logic, respectively.