Title :
Design rule centring for row redundant content addressable memories
Author :
Noghani, B. ; Jalowiecki, I.P.
Author_Institution :
Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
Abstract :
A yield model is developed to estimate yield values for an associative processing chip based largely on content addressable memory (CAM). The yield model combines analysis of a row redundant strategy for the CAM with a relaxation of design rules to minimise column defects
Keywords :
VLSI; content-addressable storage; integrated memory circuits; redundancy; CAM; associative processing chip; column defects; row redundant content addressable memories; row redundant strategy; yield model; yield values; Associative memory; Associative processing; CADCAM; Computer aided manufacturing; Fault tolerance; Integrated circuit modeling; Integrated circuit yield; Read-write memory; Redundancy; Yield estimation;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on
Conference_Location :
Dallas, TX
Print_ISBN :
0-8186-2837-5
DOI :
10.1109/DFTVS.1992.224353
