PLA decomposition to reduce the cost of concurrent checking

Author

Wessels, David ; Muzio, Jon C.

Author_Institution

Victoria Univ., BC, Canada

fYear

1992

fDate

4-6 Nov 1992

Firstpage

117

Lastpage

126

Abstract

Proposes a combination of PLA decomposition and unidirectional error detecting techniques which permits concurrent testing for all single faults in a circuit (both in the decomposed modules and on the interconnection lines), for a lower area overhead cost than is normally associated with unidirectional error detecting codes

Keywords

error detection; fault location; logic arrays; logic testing; PLA decomposition; area overhead cost; concurrent checking; decomposed modules; interconnection lines; single faults; unidirectional error detecting techniques; Circuit faults; Circuit testing; Code standards; Costs; Electrical fault detection; Fault detection; Integrated circuit interconnections; Partitioning algorithms; Programmable logic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on

Conference_Location

Dallas, TX

ISSN

1550-5774

Print_ISBN

0-8186-2837-5

Type

conf

DOI

10.1109/DFTVS.1992.224375

Filename

224375

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3211080