DocumentCode
3211213
Title
Stress modeling of Cu/low-k BEoL - application to stress migration
Author
Zhai, C.J. ; Yao, H.W. ; Besser, P.R. ; Marathe, A. ; Blish, R.C., II ; Erb, D. ; Hau-Riege, C. ; Taylor, Stephen ; Taylor, K.O.
Author_Institution
Adv. Micro Devices Inc., Sunnyvale, CA, USA
fYear
2004
fDate
25-29 April 2004
Firstpage
234
Lastpage
239
Abstract
Stress migration (SM) or stress-induced voiding (SIV) experiments were conducted for two BEoL (Back End of Line) technologies: Cu/FTEOS and Cu/Low-k. Experiments have shown the mean time to failure (MTF) depends on ILD (interlayer dielectric) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using Finite Element Analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD (inter-layer dielectric) properties, ILD stack and metal line width. The concept of a SM Risk Index is proposed to assess BEoL stress migration reliability from the stress perspective. Comparison of the SM Risk Index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.
Keywords
copper; electromigration; finite element analysis; integrated circuit interconnections; integrated circuit metallisation; stress analysis; Back End of Line; Cu; Cu/low-k BEoL; Finite Element Analysis; interlayer dielectric; mean time to failure; metal line width; process steps; process-oriented modeling approach; stack; stress evolution; stress migration; stress migration reliability; stress modeling; stress-induced voiding; via-chain test structure; Dielectrics; Finite element methods; Life estimation; Performance evaluation; Power system modeling; Samarium; Stress measurement; Temperature; Testing; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International
Print_ISBN
0-7803-8315-X
Type
conf
DOI
10.1109/RELPHY.2004.1315329
Filename
1315329
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