An approach to design-for-testability for memory embedding logic LSIs

Author

Hatayama, Kazumi ; Hayashi, Terumine ; Takakura, Masahiro ; Suzuki, Takeshi ; Michishita, Satoshi ; Satoh, Hiroyuki

fYear

1992

fDate

26-27 Nov 1992

Firstpage

212

Lastpage

217

Abstract

The authors present a design-for-testability approach to logic LSIs which are embedding random-access-memories (RAMs). This approach uses scannable RAMs for enhancing the testability of not only the RAMs themselves but also their peripheral circuits. Automatic test generation is applicable for both the RAMs and the whole logic circuit

Keywords

design for testability; integrated logic circuits; large scale integration; random-access storage; automatic test generation; design-for-testability; memory embedding logic LSIs; scan shift design; scannable RAMs; Circuit testing; Clocks; Control systems; Large scale integration; Logic circuits; Logic design; Logic testing; Pins; Signal design; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)

Conference_Location

Hiroshima

Print_ISBN

0-8186-2985-1

Type

conf

DOI

10.1109/ATS.1992.224406

Filename

224406

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3211367