Title :
Synthesis of easily testable sequential circuits with checking sequences
Author :
Shibatani, Satoshi ; Kinoshita, Kozo
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
Abstract :
A method for synthesizing sequential circuits with testability in the level of state transition table is proposed. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. By using suitable state assignment codes sequential circuits with shorter test sequences and with fewer gates are realized. Some experimental results for small benchmark circuits are shown
Keywords :
design for testability; logic design; performance evaluation; sequential circuits; state assignment; benchmark circuits; state assignment codes; state transition table; synchronizing sequence; testable sequential circuits; transfer sequences; Circuit synthesis; Circuit testing; Design engineering; Design for testability; Logic circuits; Logic testing; Physics; Sequential analysis; Sequential circuits; Test pattern generators;
Conference_Titel :
Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
Conference_Location :
Hiroshima
Print_ISBN :
0-8186-2985-1
DOI :
10.1109/ATS.1992.224408
