A method of diagnosing logical faults in combinational circuits

The authors propose a method of diagnosing any logical fault in combinational circuits. The basic idea of the method has been obtained from an observation that only an error generated on one of the fault-nets propagates often to the primary outputs under a given test though more than one fault-net exist in the circuit under test. In this method, the fault-nets are located through a repetition of deducing candidates for each individual fault-net under the assumption of single fault-net and ascertaining which is the real one by probing. Probing internal nets is done only for finding the real fault-nets from these candidates. Consequently, it becomes possible to greatly decrease the number of probed nets. Preliminary experimental results show that fault locations are almost completely identified by probing 20% of the nets at most