Investigation of Substrate Noise Coupling and Isolation Characteristics for a 0.35UM HV CMOS Technology

Author

Pflanzl, W.C. ; Seebacher, E.

Author_Institution

Austriamicrosystems AG, Unterpremstaetten

fYear

2007

fDate

21-23 June 2007

Firstpage

429

Lastpage

432

Abstract

This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 mum HV CMOS technology (Vmax <= 120 V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate "resistor" and the DUT fixture behavior.

Keywords

CMOS integrated circuits; integrated circuit modelling; integrated circuit noise; isolation technology; ohmic contacts; power integrated circuits; HV CMOS technology; isolation characteristics; metal shielded DUT fixtures; ohmic substrate contacts; size 0.35 mum; substrate noise coupling; CMOS technology; Crosstalk; Damping; Electrical resistance measurement; Fixtures; Isolation technology; Radio frequency; Resistors; Semiconductor device modeling; Testing; HV CMOS; Isolation; Substrate coupling; guard ring;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on

Conference_Location

Ciechocinek

Print_ISBN

83-922632-9-4

Electronic_ISBN

83-922632-9-4

Type

conf

DOI

10.1109/MIXDES.2007.4286198

Filename

4286198