A low-current linearity sweet spot in HFET´S

Author

Vaitkus, R. ; Nair, Vijay ; Tehrani, S.

Author_Institution

Motorola Inc., Tempe, AZ, USA

fYear

1995

fDate

16-20 May 1995

Firstpage

523

Abstract

Planar doped HFET´s exhibit a narrow bias region of low intermodulation distortion, a linearity sweet spot, at low drain current levels. The bias condition associated with this sweet spot is shown to be near the low-current inflection point of the transconductance versus gate voltage characteristic. It is also shown that the bias condition for the sweet spot can be controlled in dual-gate HFET´s. This feature in the HFET characteristics can be exploited to design low-power front-end MMIC´s with better intercept points for applications in wireless communications.<>

Keywords

field effect MMIC; integrated circuit noise; intermodulation distortion; microwave field effect transistors; drain current levels; intermodulation distortion; low-current inflection point; low-current linearity; low-power front-end MMIC; narrow bias region; planar doped HFET; transconductance versus gate voltage characteristic; wireless communications; Distortion measurement; HEMTs; Intermodulation distortion; Linearity; MODFETs; Noise figure; System testing; Transconductance; Voltage; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 1995., IEEE MTT-S International

Conference_Location

Orlando, FL, USA

ISSN

0149-645X

Print_ISBN

0-7803-2581-8

Type

conf

DOI

10.1109/MWSYM.1995.406033

Filename

406033