Title :
Delay fault testability evaluation through timing simulation
Author :
Bose, Soumitra ; Agrawal, Prathima ; Agrawal, Vishwani D.
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
For a given set of vectors, the guaranteed failure frequency of a synchronous sequential circuit is defined. This frequency is obtained from multiple delay logic simulation by selectively suppressing timing hazards. Any path delay fault testable by the vectors, if present, is guaranteed to be detected if the tests were run at this frequency
Keywords :
delays; digital simulation; fault location; logic CAD; sequential circuits; failure frequency; multiple delay logic simulation; path delay fault; synchronous sequential circuit; testability evaluation; timing hazards; timing simulation; Circuit faults; Circuit simulation; Circuit testing; Delay; Electrical fault detection; Frequency; Hazards; Logic; Sequential circuits; Timing;
Conference_Titel :
VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-3430-8
DOI :
10.1109/GLSV.1993.224489
