Chip-level ESD simulation for fail detection and design guidance

Modern VLSI designs in deep submicron technologies constitute a new type of ESD protection challenge. Increasing complexity of modem digital and mixed signal designs demands for simulation and verification methods that guarantee, that ESD protection concepts and rules are correctly implemented and brought to silicon. A simulation approach and analysis method is presented that allows to address a class of ESD fails caused not by specific design or layout errors, but rather by an unfavourable setup of the chip supply concept and I/O cell ring. The high complexity of chip-level ESD networks is handled with a Monte-Carlo like, permutational approach. The integration of this method in the chip concept engineering and design flow is discussed.