Recent advances in test planning for modular testing of core-based SOCs

Author

Iyengar, Vikram ; Chakrabarty, Krishnendu ; Marinissen, Erik Jan

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

2002

fDate

18-20 Nov. 2002

Firstpage

320

Lastpage

325

Abstract

Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper we survey recent advances in test planning that address the problems of test access and constrained test scheduling for core-based SOCs. We describe several test access architectures proposed by research groups in industry and academia, as well as a wide range of methodologies for the optimization of such architectures. An extensive list of references to prior and current work in the SOC test planning domain is included.

Keywords

automatic test equipment; circuit optimisation; constraint handling; design for testability; integrated circuit design; integrated circuit economics; integrated circuit testing; logic design; logic testing; planning; system-on-chip; ATE; DFT; SOC test planning advances; TAM; constrained test scheduling; core-based SOC modular testing; core-based system-on-a-chip designs; test access architectures optimization; test access mechanisms; test cost reduction; testing time reduction; Costs; Design optimization; Hip; Laboratories; Logic testing; Microelectronics; Pins; System testing; System-on-a-chip; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian

ISSN

1081-7735

Print_ISBN

0-7695-1825-7

Type

conf

DOI

10.1109/ATS.2002.1181731

Filename

1181731