A method to reduce power dissipation during test for sequential circuits

For recent VLSIs designed for low power, reduction of power dissipation during test is one of the most important problems. This paper presents a method to reduce power dissipation during test for sequential circuits. The goal is to obtain test vectors for sequential circuits that achieve low power dissipation. In our method, test vectors generated by ATPG are given and they are improved to reduce power dissipation without losing the original stuck-at fault coverage. Due to the correlation between power dissipation and the number of transition gates, the number of transition gates is evaluated for each test vector during modification of test vectors. In order to keep the original fault coverage, logic simulation and fault simulation are performed, every time a test vector is modified. The effectiveness of our method is shown by experimental results for ISCAS ´89 benchmark circuits.