Efficient hardware implementation for 802.16e double binary Turbo decoder

In this paper, a hardware implementation of 802.16e-2005 Turbo encoder and decoder is presented with an efficient interleaver implementation and normalization scheme. The normalization scheme is based on rescaling, which results in area and memory reduction and speed enhancement. It is shown that this normalization technique saves up to 12% of the required storage in addition to saving hardware resources needed for the decoding operation. A speed efficient implementation for this normalization which reduces critical path delay up to 16.5% using redundant number system is proposed.