DocumentCode :
3214041
Title :
Placement algorithm for multiplier-based FPGA circuits
Author :
Athow, Jacques L. ; Al-Khalili, Asim J.
Author_Institution :
Dept of Electr. & Comput. Eng., Concordia Unviersity, Montreal, QC, Canada
fYear :
2008
fDate :
14-17 Dec. 2008
Firstpage :
167
Lastpage :
170
Abstract :
FPGA placement algorithms have stricter location constraints compared to normal ASIC placers. For large circuits, designers often start by using a best local solution and iterate until a reasonable global solution is attained, with optimization criteria such as minimum delay, area and power. This paper presents a modified greedy algorithm for placing Xilinx FPGA blocks, specifically designed for large multipliers. The solution decreases die utilization by aligning pipeline registers in an optimal way with respect to DSP48 blocks, hence decreasing delay, routing interconnect and consequently total power consumption of the design. Placement of long-integer multipliers with the proposed algorithm can result in delay reduction of up to 20%.
Keywords :
field programmable gate arrays; greedy algorithms; integrated circuit interconnections; integrated circuit layout; delay; modified greedy algorithm; multiplier-based FPGA circuits; placement algorithm; routing interconnect; total power consumption; Algorithm design and analysis; Application specific integrated circuits; Delay; Design optimization; Energy consumption; Field programmable gate arrays; Greedy algorithms; Integrated circuit interconnections; Pipelines; Routing; DSP48; FPGA; Floorplanning; multiplier; placement algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics, 2008. ICM 2008. International Conference on
Conference_Location :
Sharjah
Print_ISBN :
978-1-4244-2369-9
Electronic_ISBN :
978-1-4244-2370-5
Type :
conf
DOI :
10.1109/ICM.2008.5393533
Filename :
5393533
Link To Document :
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