A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement

Author

Chao-Chang Chiu ; Po-Hsien Huang ; Lin, Man ; Ke-Horng Chen ; Ying-Hsi Lin ; Tsung-Yen Tsai ; Chen Chao-Cheng Lee

Author_Institution

Inst. of Electr. Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

62

Issue

1

fYear

2015

fDate

Jan. 2015

Firstpage

59

Lastpage

69

Abstract

The proposed resistance-locked loop (RLL) can achieve high PSRR of -16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.

Keywords

CMOS digital integrated circuits; digital control; elemental semiconductors; integrated circuit testing; microcontrollers; power integrated circuits; silicon; stability; transistor circuits; voltage regulators; CMOS process; DLDO regulator; DLDO stability; PSRR; Si; core device; duty compensator; embedded digital low dropout regulator; peak current efficiency; power saving; power supply rejection; resistance-locked loop; silicon area; size 40 nm; voltage 0.6 V; Arrays; MOSFET; Modulation; Noise; Regulators; Switches; Voltage control; Current efficiency; digital low dropout (DLDO) regulator; resistance-locked loop (RLL);

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2014.2342380

Filename

6879504