DocumentCode
3215488
Title
The quasi-Booth multiplier
Author
Dadda, Luigi ; Piuri, Vincenzo ; Salice, Fabio
Author_Institution
Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
fYear
1996
fDate
9-11 Oct 1996
Firstpage
36
Lastpage
45
Abstract
A new approach to number representation is presented to implement fast parallel multipliers: the operands are given in a signed-digit representation, similar to the one proposed by Booth. With respect to a multiplier based on the Booth´s notation, our approach allows one to save circuit complexity and, as a consequence, silicon area (up to 20% for the partial product generator)
Keywords
digital arithmetic; logic design; multiplying circuits; parallel architectures; circuit complexity; fast parallel multipliers; number representation; partial product generator; quasi-Booth multiplier; signed-digit representation; silicon area; Adders; Complexity theory; Computer networks; Concurrent computing; Delay; Hardware; Integrated circuit interconnections; Iterative algorithms; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Systems in Silicon, 1996. Proceedings., Eighth Annual IEEE International Conference on
Conference_Location
Austin, TX
ISSN
1063-2204
Print_ISBN
0-7803-3639-9
Type
conf
DOI
10.1109/ICISS.1996.552409
Filename
552409
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