DocumentCode
3215717
Title
A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps
Author
Leyn, F. ; Daems, W. ; Gielen, G. ; Sansen, W.
Author_Institution
Katholieke Univ., Leuven, Belgium
fYear
1997
fDate
9-13 Nov. 1997
Firstpage
374
Lastpage
381
Abstract
This paper describes a new modeling methodology that allows to derive systematically behavioral signal path models of operational amplifiers. Combined with symbolic simulation, these models provide high qualitative insight into the small-signal functioning of a circuit. The behavioral signal path model provides compact interpretable expressions for the poles and zeros that constitute the signal path. These expressions show which design parameters have dominant influence on the position of a pole/zero and thus enable a designer to control a manual interactive sizing process. The methodology consists of the application of a sequence of abstractions, so that one gradually progresses from a full device to a full behavior circuit representation. During this translation, qualitative insight and design requirements are obtained. The methodology is implemented in an open tool called EF2ef. The behavioral signal path model is also used for optimization based sizing in order to achieve pole placement in an efficient way. For optimization based siting, a new strategy for hierarchical penalty function composition is proposed, which allows sequential pruning of the design space. Combined with an operating point driven DC formulation and local minimax optimization, a fast sizing method is obtained which can be used for interactive design space exploration. Experimental results of both modeling and siting are shown.
Keywords
CMOS analogue integrated circuits; circuit CAD; circuit analysis computing; circuit optimisation; digital simulation; integrated circuit modelling; minimax techniques; operational amplifiers; poles and zeros; CAD; CMOS opamps; DC formulation; EF2ef; analog circuit modeling; behavioral signal path modeling methodology; circuit optimization; design parameters; design space pruning; hierarchical penalty function composition; interactive design space exploration; interactive sizing process; local minimax optimization; operational amplifiers; pole placement; poles and zeros; small-signal functioning; symbolic simulation; Operational amplifiers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-8186-8200-0
Type
conf
DOI
10.1109/ICCAD.1997.643563
Filename
643563
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