A source-line programming scheme for low voltage operation NAND flash memories

Author

Takeuchi, K. ; Satoh, S. ; Imamiya, K. ; Sugiura, Y. ; Nakamura, H. ; Himeno, T. ; Ikehashi, T. ; Kanda, K. ; Hosono, K. ; Sakui, K.

Author_Institution

Lab. of Microelectron. Eng., Toshiba Corp., Yokohama, Japan

fYear

1999

fDate

17-19 June 1999

Firstpage

37

Lastpage

38

Abstract

The increasing demand for low voltage/low power portable equipment in the consumer marketplace has created a need for a low voltage/low power flash memory. In portable communication products, sub-1.8 V operation is essential. In view of the chip cost, a NAND-type cell has a big advantage over a NOR-type cell due to its smaller cell size. However, in this paper we show for the first time that the conventional NAND flash memory cannot operate below 2.0 V due to a program disturb issue. To solve this problem, we propose a new programming scheme which drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories.

Keywords

NAND circuits; flash memories; high-speed integrated circuits; low-power electronics; 2.0 V; NAND flash memory; high-speed cell; low power portable communication equipment; low voltage operation; program disturb; source-line programming; Boosting; Capacitance; Costs; Electrons; Energy consumption; Flash memory; Laboratories; Low voltage; Microelectronics; Power engineering and energy;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797227

Filename

797227