Safety of VLSI designs using VHDL

This paper presents a methodology associated to a software tool to generate fail-safe VHDL synthesizable descriptions from Petri net or state diagrams. With this philosophy of automatically providing safety to VLSI systems design in VHDL, designers do not have to include the error detection system because it is going to be added automatically in the design. The method is explained as a group of sequential steps that transform a system into a fail-safe one. The tool uses a graphical environment to define the Petri net or state diagram. VHDL was chosen because is a standard widely supported by synthesis tools. The implementation of the circuit, which is valid either for programmable logic or ASICs, is done by other tools that support the VHDL standard. Following this methodology, three design parameters appear: size (consumption), speed, and safety level. Usually, every tool presents only optimization by speed and size. The proposed tool is fully implemented. VHDL code is synthesizable and experiments were made comparing unsafe and fail-safe systems in relation to their defining characteristics. Adding safety obviously supposes a heavy penalty in area occupied by the circuit. Future work should study the combination of other safety mechanisms, including the possibility of establishing a flexible level of safety.