A 550-ps access, 900-MHz, 1-Mb ECL-CMOS SRAM

Author

Nambu, H. ; Kanetani, K. ; Yamasaki, K. ; Higeta, K. ; Usami, M. ; Nishiyama, M. ; Ohhata, K. ; Arakawa, F. ; Kusunoki, T. ; Yamaguchi, K. ; Homma, N.

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

fYear

1999

fDate

17-19 June 1999

Firstpage

111

Lastpage

112

Abstract

Summary form only given. An ultra-high-speed 1 Mb ECL-CMOS SRAM with 550 ps access time and 900 MHz operating frequency has been developed using 0.2 /spl mu/m BiCMOS technology. Three key techniques for achieving the high speed are a BiCMOS word driver with an NMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable impedance load of a bit line.

Keywords

BiCMOS memory circuits; SRAM chips; emitter-coupled logic; very high speed integrated circuits; 0.2 micron; 1 Mbit; 550 ps; 900 MHz; BiCMOS technology; BiCMOS word driver; BiCMOS write circuit; ECL-CMOS SRAM; NMOS level-shift circuit; sense amplifier; ultra-high-speed operation; variable impedance load; voltage-clamp circuit; BiCMOS integrated circuits; CMOS memory circuits; Cache memory; Delay effects; Driver circuits; Impedance; MOSFETs; Power dissipation; Random access memory; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-95-6

Type

conf

DOI

10.1109/VLSIC.1999.797254

Filename

797254

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3216846